Top 100 - Static Storage

US5644539 (A), filed Wed Nov 25 00:00:00 CST 1992 , published Tue Jul 01 00:00:00 CDT 1997 - HITACHI LTD

A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, said semiconductor disk comprises a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors...

Device and method for repairing a memory array by storing each bit in multiple memory cells in the array

US5781483 (A), filed Tue Dec 31 00:00:00 CST 1996 , published Tue Jul 14 00:00:00 CDT 1998 - MICRON TECHNOLOGY INC

A DRAM array is repairable when the array includes memory cells that are defective because their storage capacitors are unable to retain a sufficient electric charge to properly store "1" and "0" bits. To repair the array, both even and odd row decoders in the...

Non-volatile memory device and refreshing method

US6459614 (B1), filed Wed Dec 19 00:00:00 CST 2001 , published Tue Oct 01 00:00:00 CDT 2002 - HITACHI LTD

At the data programming, plural data bit is transformed by a data transforming logic circuit into multi-value data according to the combination of bits, and the transformed data are sequentially transferred to a latch circuit connected to bit lines of a memory...

Content addressable memory with error detection signaling

US6597595 (B1), filed Tue Sep 18 00:00:00 CDT 2001 , published Tue Jul 22 00:00:00 CDT 2003 - NETLOGIC MICROSYSTEMS INC

A content addressable memory (CAM) device having a data CAM array and an error CAM array. The data CAM array is provided to store data words, compare the data words with a comparand value, and, if one of the data words matches the comparand value, assert a...

Self-timed bootstrap decoder

US5327026 (A), filed Wed Feb 17 00:00:00 CST 1993 , published Tue Jul 05 00:00:00 CDT 1994 - UNITED MEMORIES INC

A row decoder that includes circuitry to provide a self-timed bootstrap signal. The self-timed bootstrap signal is generated in response to the selection of the row decoder. At the same time, a capacitive device is charged in order to bootstrap a word line....

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure

US6507885 (B2), filed Thu Feb 03 00:00:00 CST 2000 , published Tue Jan 14 00:00:00 CST 2003 - MICRON TECHNOLOGY INC

A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is organized into multiple main blocks each having multiple smaller blocks, emulating a disk drive....

Semiconductor memory

US4472792 (A), filed Thu May 13 00:00:00 CDT 1982 , published Tue Sep 18 00:00:00 CDT 1984 - HITACHI LTD

A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of...

Nonvolatile semiconductor memory with a plurality of erase decoders connected to erase gates

US5761119 (A), filed Tue Jul 12 00:00:00 CDT 1994 , published Tue Jun 02 00:00:00 CDT 1998 - TOKYO SHIBAURA ELECTRIC CO

A non-volatile semiconductor memory cell including: a plurality of blocks each having a plurality of floating gate transistors as memory cells, the floating gate transistor having a drain, a source, a floating gate, and a control gate capacitively coupled to...

Microcomputer with high density RAM on single chip

US6414368 (B1), filed Tue Mar 03 00:00:00 CST 1998 , published Tue Jul 02 00:00:00 CDT 2002 - SGS THOMSON MICROELECTRONICS

A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit...

Magnetic spin transistor device, logic gate method of operation

US5629549 (A), filed Fri Apr 21 00:00:00 CDT 1995 , published Tue May 13 00:00:00 CDT 1997

A new magnetic spin transistor is provided. This spin transistor can be used as a memory element or logic gate, such as an OR, AND, NOT, NOR and NAND gate. The state of the magnetic spin transistor logic gate is set inductively. This new magnetic spin...

Boundary scan cell for bi-directional input/output terminals

US5220281 (A), filed Tue Jan 28 00:00:00 CST 1992 , published Tue Jun 15 00:00:00 CDT 1993 - TOKYO SHIBAURA ELECTRIC CO

A boundary scan cell is disclosed. Bi-directional input/output terminals are connected to bi-directional input/output terminals of a logic circuit subject to test in order to store test data or a test result in a first latch circuit, the output impedance of...

Built-in self-test arrangement for integrated circuit memory devices

US6801461 (B2), filed Mon Dec 17 00:00:00 CST 2001 , published Tue Oct 05 00:00:00 CDT 2004 - TEXAS INSTRUMENTS INC

An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read...

Content addressable memory having dual access modes

US4646271 (A), filed Wed Dec 19 00:00:00 CST 1984 , published Tue Feb 24 00:00:00 CST 1987 - HITACHI LTD

In a memory device having a content addressable memory array and a random access memory array, the word coincidence lines and word selection lines of the content addressable memory array are connected to the word selection lines of the corresponding words of...

No title available

US4646271 (B1), filed Wed Dec 19 00:00:00 CST 1984 , published Tue Aug 03 00:00:00 CDT 1993 - HITACHI LTD

Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom

US5534711 (A), filed Wed Apr 19 00:00:00 CDT 1995 , published Tue Jul 09 00:00:00 CDT 1996 - ENERGY CONVERSION DEVICES INC

The present invention comprises an electrically operated, directly overwritable, multibit, single-cell memory element. The memory element includes a volume of memory material which defines the single cell memory element. The memory material is characterized...

Semiconductor memory

US5966341 (A), filed Tue Dec 02 00:00:00 CST 1997 , published Tue Oct 12 00:00:00 CDT 1999 - HITACHI LTD

A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells...

Digit line architecture for dynamic memory

US6043562 (A), filed Thu Aug 22 00:00:00 CDT 1996 , published Tue Mar 28 00:00:00 CST 2000 - MICRON TECHNOLOGY INC

A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6 F2 or...

Computerized machine control system

US4364110 (A), filed Wed Jun 05 00:00:00 CDT 1974 , published Tue Dec 14 00:00:00 CST 1982 - HYATT GILBERT P

An improved machine control system having a display for operator interaction is provided. Feedback machine control is provided with an integrated circuit computer. Display of edges having rotation, translation, scaling, and smoothing is also provided.

Embedded access trees for memory arrays

US5570319 (A), filed Thu Aug 31 00:00:00 CDT 1995 , published Tue Oct 29 00:00:00 CST 1996 - SUN MICROSYSTEMS INC

An improved approach for breaking the bit lines of a semiconductor memory device into small pieces, referred to herein as Embedded Access Trees (EATs), is introduced. Embedded Access Trees enjoy the principal advantage of the banked approach by dividing long...

ELECTRICALLY ERASABLE PHASE CHANGE MEMORY

US5166758 (A), filed Fri Jan 18 00:00:00 CST 1991 , published Tue Nov 24 00:00:00 CST 1992 - ENERGY CONVERSION DEVICES INC

Multi-state memory

US6222762 (B1), filed Thu Aug 07 00:00:00 CDT 1997 , published Tue Apr 24 00:00:00 CDT 2001 - SANDISK CORP

Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on...

Programmable microelectronic devices and method of forming and programming same

US6487106 (B1), filed Fri Feb 11 00:00:00 CST 2000 , published Tue Nov 26 00:00:00 CST 2002 - UNIV ARIZONA

A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally include an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by...

Triangular semiconductor or gate

US6097073 (A), filed Mon Aug 21 00:00:00 CDT 1995 , published Tue Aug 01 00:00:00 CDT 2000 - LSI LOGIC CORP

Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other...

Substrate coupled floating gate memory cell

US4274012 (A), filed Wed Jan 24 00:00:00 CST 1979 , published Tue Jun 16 00:00:00 CDT 1981 - XICOR INC

Nonvolatile semiconductor electrically-alterable, floating-gate memory methods and devices which utilize substrate coupling for self-regulated, tunnel-current-shaping to provide improved device characteristics. The substrate coupling also facilitates the cell...

Flash eeprom system with defect handling

US5671229 (A), filed Wed May 25 00:00:00 CDT 1994 , published Tue Sep 23 00:00:00 CDT 1997 - SANDISK CORP

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased...

Methods for producing composites of single-wall carbon nanotubes and compositions thereof

US7105596 (B2), filed Fri Dec 28 00:00:00 CST 2001 , published Tue Sep 12 00:00:00 CDT 2006 - UNIV RICE WILLIAM M

This invention relates generally to a method for producing composites of single-wall carbon nanotubes (SWNTs) and compositions thereof. In one embodiment, the present invention involves a method of producing a composite material that includes a matrix and a...

Semiconductor memory device having diagnostic circuit for comparing multi-bit read-out test data signal with multi-bit write-in test data signal stored in serial-input shift register

US5406566 (A), filed Fri Oct 22 00:00:00 CDT 1993 , published Tue Apr 11 00:00:00 CDT 1995 - NIPPON ELECTRIC CO

A dynamic random access memory device is subjected to a diagnosis upon completion of fabrication to see whether or not a defective memory cell is incorporated in memory cell sub-arrays, one of the input/output data buffer circuits incorporated therein...

Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems

US5663901 (A), filed Tue Sep 12 00:00:00 CDT 1995 , published Tue Sep 02 00:00:00 CDT 1997 - SANDISK CORP

A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces...

High permeability composite films to reduce noise in high speed interconnects

US6846738 (B2), filed Wed Mar 13 00:00:00 CST 2002 , published Tue Jan 25 00:00:00 CST 2005 - MICRON TECHNOLOGY INC

This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated circuit. The method includes forming a first layer of electrically...

Memory architecture with single-port cell and dual-port (read and write) functionality

US6411557 (B2), filed Fri Feb 02 00:00:00 CST 2001 , published Tue Jun 25 00:00:00 CDT 2002 - BROADCOM CORP

A single-port hierarchical memory structure including memory modules having memory cells; hierarchically-coupled local and global sense amplifiers; hierarchically-coupled local and global row decoders; and a predecoding circuit coupled with selected global row...

Content addressable memory device

US6697276 (B1), filed Fri Feb 01 00:00:00 CST 2002 , published Tue Feb 24 00:00:00 CST 2004 - NETLOGIC MICROSYSTEMS INC

A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a compare circuit. The index generator generates an index based on the search value. The memory receives...

Programmable logic device

US4761768 (A), filed Mon Mar 04 00:00:00 CST 1985 , published Tue Aug 02 00:00:00 CDT 1988 - LATTICE SEMICONDUCTOR CORP

An improved programmable logic device (PLD) is disclosed which employs electrically erasable memory cells which can be programmed and erased at high speed. The PLD memory cells comprise floating gate transistors as the storage elements, which are programmed...

Methods for saving power and area for content addressable memory devices

US7064971 (B2), filed Mon Jan 05 00:00:00 CST 2004 , published Tue Jun 20 00:00:00 CDT 2006 - SHAU JENG-JYE

Using 6 transistor memory cell to replace prior art 10 transistor binary content addressable memory (CAM) cells, and using 10 transistor ternary CAM (TCAM) cell to replace prior art 16 transistor TCAM cells, the present invention provided significant cost...

Reprogrammable subscriber terminal

US6212278 (B1), filed Wed Jun 07 00:00:00 CDT 1995 , published Tue Apr 03 00:00:00 CDT 2001 - SCIENTIFIC ATLANTA

A reprogrammable subscriber terminal of a subscription television service which can have the control program code of its control processor modified by downloading new program code from the headend. The control processor stores a boot program in an internal...

Active programmable electronic devices for molecular biological analysis and diagnostics

US5605662 (A), filed Mon Nov 01 00:00:00 CST 1993 , published Tue Feb 25 00:00:00 CST 1997 - NANOGEN INC

A self-addressable, self-assembling microelectronic device is designed and fabricated to actively carry out and control multi-step and multiplex molecular biological reactions in microscopic formats. These reactions include nucleic acid hybridization,...

Semiconductor memory

US4539658 (A), filed Wed Aug 08 00:00:00 CDT 1984 , published Tue Sep 03 00:00:00 CDT 1985 - HITACHI LTD

A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of...

Carbon fibers formed from single-wall carbon nanotubes

US6683783 (B1), filed Wed Dec 22 00:00:00 CST 1999 , published Tue Jan 27 00:00:00 CST 2004 - UNIV RICE WILLIAM M

A method for purifying a mixture comprising single-wall carbon nanotubes and amorphous carbon contaminate is disclosed. The method includes the steps of heating the mixture under oxidizing conditions sufficient to remove the amorphous carbon, followed by...

Low cross-talk electrically programmable resistance cross point memory

US6693821 (B2), filed Thu Jun 28 00:00:00 CDT 2001 , published Tue Feb 17 00:00:00 CST 2004 - SHARP LAB OF AMERICA INC

Low cross talk resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises a bit formed using a perovskite material interposed at a cross point of an upper electrode and lower electrode. Each bit...

EEPROM with split gate source side injection

US5712180 (A), filed Wed Feb 28 00:00:00 CST 1996 , published Tue Jan 27 00:00:00 CST 1998 - SUNDISK CORP

Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In...

Electrically programmable nonvolatile semiconductor memory device with NAND cell structure

US5008856 (A), filed Tue Jun 28 00:00:00 CDT 1988 , published Tue Apr 16 00:00:00 CDT 1991 - TOKYO SHIBAURA ELECTRIC CO

Hexagonal architecture

US6407434 (B1), filed Mon Aug 21 00:00:00 CDT 1995 , published Tue Jun 18 00:00:00 CDT 2002 - LSI LOGIC CORP

Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other...

Magnetic spin transistor hybrid circuit element

US5565695 (A), filed Thu Jun 22 00:00:00 CDT 1995 , published Tue Oct 15 00:00:00 CDT 1996

A new nonvolatile hybrid memory cell is provided. The cell is comprised of a magnetic spin transistor storage element and one or two FET isolation elements. The magnetic spin transistor stores data indefinitely while drawing zero quiescent power. The FET is...

Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein

US5768194 (A), filed Wed Jun 07 00:00:00 CDT 1995 , published Tue Jun 16 00:00:00 CDT 1998 - HITACHI LTD

A single chip semiconductor integrated circuit device having a central processing unit (CPU) and a flash memory which stores data to be processed by the CPU and which provides data to the CPU through the data bus in response to accessing instructions from the...

Sense amplifier for use in an EEPROM

US5740112 (A), filed Thu Jan 04 00:00:00 CST 1996 , published Tue Apr 14 00:00:00 CDT 1998 - TOKYO SHIBAURA ELECTRIC CO

A sense amplifier for signal detection for use in an electrically erasable and programmable read-only memory (EEPROM). The sense amplifier includes a first clock signal-synchronized inverter including a first inverter and first switch for switching between...

Semiconductor integrated circuit device and method of activating the same

US5724297 (A), filed Thu Dec 12 00:00:00 CST 1996 , published Tue Mar 03 00:00:00 CST 1998 - HITACHI LTD

A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block,...

Semiconductor device having bipolar transistor and insulated gate field effect transistor with two potential power source

US4730132 (A), filed Fri Jul 18 00:00:00 CDT 1986 , published Tue Mar 08 00:00:00 CST 1988 - HITACHI LTD

Method and apparatus for address translation in a partitioned content addressable memory device

US6763425 (B1), filed Thu Jun 08 00:00:00 CDT 2000 , published Tue Jul 13 00:00:00 CDT 2004 - NETLOGIC MICROSYSTEMS INC

A CAM device having plurality of CAM blocks includes circuitry to disable one or more defective CAM blocks, and to selectively translate address space in the disabled CAM blocks to the remaining enabled CAM blocks. In one embodiment, each CAM block is coupled...

Vertically stacked field programmable nonvolatile memory and method of fabrication

US6034882 (A), filed Mon Nov 16 00:00:00 CST 1998 , published Tue Mar 07 00:00:00 CST 2000 - MATRIX SEMICONDUCTOR INC

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps...

Electrostatic discharge protection systems and methods for electronic tokens

US5920096 (A), filed Thu Dec 01 00:00:00 CST 1994 , published Tue Jul 06 00:00:00 CDT 1999 - DALLAS SEMICONDUCTOR

A system architecture which provides efficient data communication, over a one-wire bus, with a portable data module which does not necessarily include any accurate time delay circuit whatsoever. The time delay circuit in the module can be extremely crude. An...

Latched sense amplifiers as high speed memory in a memory system

US6717864 (B2), filed Tue Oct 15 00:00:00 CDT 2002 , published Tue Apr 06 00:00:00 CDT 2004 - MONLITHIC SYSTEM TECHNOLOGY IN

A memory system includes a plurality of memory modules, each including at least one memory array. Each memory array has an associated line of sense amplifier latches, wherein each line of sense amplifier latches is activated independently. Each line of sense...

Electrically programmable and erasable nonvolatile semiconductor memory device and operating method therefor

US5898606 (A), filed Wed Apr 30 00:00:00 CDT 1997 , published Tue Apr 27 00:00:00 CDT 1999 - MITSUBISHI ELECTRIC CORP

In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a...

Built-in self-test arrangement for integrated circuit memory devices

US6353563 (B1), filed Mon Mar 15 00:00:00 CST 1999 , published Tue Mar 05 00:00:00 CST 2002 - TEXAS INSTRUMENTS INC

An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read...

Method of compensating for a defect within a semiconductor device

US6600687 (B2), filed Mon Sep 23 00:00:00 CDT 2002 , published Tue Jul 29 00:00:00 CDT 2003 - MICRON TECHNOLOGY INC

As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's...

Built-in self-test arrangement for integrated circuit memory devices

US5883843 (A), filed Wed Apr 30 00:00:00 CDT 1997 , published Tue Mar 16 00:00:00 CST 1999 - TEXAS INSTRUMENTS INC

An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read...

Programmable logic array integrated circuits

US5550782 (A), filed Wed May 18 00:00:00 CDT 1994 , published Tue Aug 27 00:00:00 CDT 1996 - ALTERA CORP

A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided...

Method and device for encoding product and programming information in semiconductors

US4451903 (A), filed Fri Sep 18 00:00:00 CDT 1981 , published Tue May 29 00:00:00 CDT 1984 - SEEQ TECHNOLOGY INC

A method and system for encoding key product information in semiconductors is disclosed. The invention is particularly useful in connection with byte-wide memories, but also finds application in a wide range of semiconductor devices. A plurality of read only...

Burst EDO memory device

US5526320 (A), filed Fri Dec 23 00:00:00 CST 1994 , published Tue Jun 11 00:00:00 CDT 1996 - MICRON TECHNOLOGY INC

An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the...

SIMD array processing system with routing networks having plurality of switching stages to transfer messages among processors

US4985832 (A), filed Thu Sep 18 00:00:00 CDT 1986 , published Tue Jan 15 00:00:00 CST 1991 - DIGITAL EQUIPMENT CORP

An array processing system including a plurality of processing elements each including a processor and an associated memory module, the system further including a router network over which each processing element can transfer messages to other random...

Semiconductor integrated circuit device

US7336535 (B2), filed Wed Mar 28 00:00:00 CDT 2007 , published Tue Feb 26 00:00:00 CST 2008 - HITACHI ULSI SYS CO LTD

A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part...

Electrically programmable resistance cross point memory

US6531371 (B2), filed Thu Jun 28 00:00:00 CDT 2001 , published Tue Mar 11 00:00:00 CST 2003 - SHARP LAB OF AMERICA INC

Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active...

Semiconductor memory

US4739497 (A), filed Mon Sep 17 00:00:00 CDT 1984 , published Tue Apr 19 00:00:00 CDT 1988 - HITACHI LTD

A semiconductor memory is provided which includes a plurality of data lines, a plurality of word lines which are arranged so as to intersect the plurality of data lines, and a plurality of memory cells which are respectively disposed at intersection points...

Large scale integrated circuit with sense amplifier circuits for low voltage operation

US5526313 (A), filed Tue Aug 10 00:00:00 CDT 1993 , published Tue Jun 11 00:00:00 CDT 1996 - HITACHI LTD

Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power...

Nonvolatile memory system, semiconductor memory and writing method

US5982668 (A), filed Tue Aug 18 00:00:00 CDT 1998 , published Tue Nov 09 00:00:00 CST 1999 - HITACHI LTD

A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each...

Non-volatile semiconductor memory device and memory system using the same

US5361227 (A), filed Fri Dec 18 00:00:00 CST 1992 , published Tue Nov 01 00:00:00 CST 1994 - TOKYO SHIBAURA ELECTRIC CO

The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations,...

Large scale integrated circuit with sense amplifier circuits for low voltage operation

USRE40132 (E1), filed Fri May 25 00:00:00 CDT 2001 , published Tue Mar 04 00:00:00 CST 2008 - ELPIDA MEMORY INC

Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power...

Integrated circuit high voltage clamping systems

US4533846 (A), filed Thu May 27 00:00:00 CDT 1982 , published Tue Aug 06 00:00:00 CDT 1985 - XICOR INC

Integrated high voltage clamping methods and devices which provide a controllable "soft" clamping action. The systems are particularly useful for "on-chip" EEPROM high voltage power supplies.

Methods for electronically-controlled enzymatic reactions

US7172864 (B1), filed Mon Jan 24 00:00:00 CST 2000 , published Tue Feb 06 00:00:00 CST 2007 - NANOGEN

A self-addressable, self-assembling microelectronic device is designed and fabricated to actively carry out and control multi-step and multiplex molecular biological reactions in microscopic formats. These reactions include nucleic acid hybridizations,...

Method of reducing disturbs in non-volatile memory

US6717851 (B2), filed Wed Jan 10 00:00:00 CST 2001 , published Tue Apr 06 00:00:00 CDT 2004 - SANDISK CORP

In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect,...

Large scale integrated circuit with sense amplifier circuits for low voltage operation

USRE37593 (E1), filed Wed Jun 10 00:00:00 CDT 1998 , published Tue Mar 19 00:00:00 CST 2002 - HITACHI ULSI SYS CO LTD

Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power...

Remotely programmable matrices with memories

US5741462 (A), filed Tue Apr 25 00:00:00 CDT 1995 , published Tue Apr 21 00:00:00 CDT 1998 - IRORI

Combinations, called matrices with memories, of matrix materials with remotely addressable or remotely programmable recording devices that contain at least one data storage unit are provided. The matrix materials are those that are used in as supports in solid...

Membrane 3D IC fabrication

US7307020 (B2), filed Thu Dec 18 00:00:00 CST 2003 , published Tue Dec 11 00:00:00 CST 2007 - ELM TECHNOLOGY CORP

General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a...

Fast transmission line implemented with receiver, driver, terminator and IC arrangements

US5548226 (A), filed Thu Jun 30 00:00:00 CDT 1994 , published Tue Aug 20 00:00:00 CDT 1996 - HITACHI LTD

A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block...

Directly bonded SIMM module

USRE36325 (E), filed Tue Sep 26 00:00:00 CDT 1995 , published Tue Oct 05 00:00:00 CDT 1999 - MICRON TECHNOLOGY INC

A leadframe interconnect package is tape automated bond (TAB) bonded to circuitry on the chip and which provides a circuit connection for subsequent connection to a printed circuit board. The encapsulated chips will replace both the leadframe and printed...

Photoluminescent materials and associated process and infrared sensing device

US4830875 (A), filed Thu Jun 05 00:00:00 CDT 1986 , published Tue May 16 00:00:00 CDT 1989 - QUANTEX CORP

Photoluminescent materials useful for detection of infrared light are constructed using a base material of strontium sulfide. Barium sulfate is used to increase brightness of output light of the materials, whereas lithium floride is used to allow the material...

Multi-output multiplexor

US6798685 (B2), filed Thu Dec 26 00:00:00 CST 2002 , published Tue Sep 28 00:00:00 CDT 2004 - UNITY SEMICONDUCTOR CORP

Providing a multi-output multiplexor. The invention is multi-output multiplexor that, depending on the control signals, allows various modulating circuits to pass no voltage, pass some voltage or pass all the voltage on one of the multiplexor's ports. A...

Programmable power generation circuit for flash EEPROM memory systems

US5568424 (A), filed Wed Jun 07 00:00:00 CDT 1995 , published Tue Oct 22 00:00:00 CDT 1996 - SANDISK CORP

An flash EEPROM system functioning as a mass storage medium for a host computer includes a controller and at least one flash EEPROM memory module. The flash EEPROM memory module includes at least one flash EEPROM chip having an on-chip programmable power...

Method and apparatus for re-assigning priority in a partitioned content addressable memory device

US6687785 (B1), filed Thu Jun 08 00:00:00 CDT 2000 , published Tue Feb 03 00:00:00 CST 2004 - NETLOGIC MICROSYSTEMS INC

A method and apparatus that may be used to disable one or more defective CAM blocks, and to selectively re-assign priority between the remaining enabled CAM blocks. In one embodiment, each CAM block includes an array of CAM cells organized in a number of rows...

Device having a memory array storing each bit in multiple memory cells

US6958945 (B2), filed Fri Aug 27 00:00:00 CDT 2004 , published Tue Oct 25 00:00:00 CDT 2005 - MICRON TECHNOLOGY INC

A memory array is provided, having at least two memory cells accessed for each row address to retain a sufficient electric charge to properly store "1" and "0" bits. For such a memory array, both even and odd row decoders in the array are permanently enabled...

Method for creating defect management information in an recording medium, and apparatus and medium based on said method

US6754860 (B2), filed Fri Feb 21 00:00:00 CST 2003 , published Tue Jun 22 00:00:00 CDT 2004 - LG ELECTRONICS INC

This invention provides a method for creating/writing defect management information of an information recording medium and an apparatus and optical disc based on the method. In the present invention, it depends on the type of data to be reproduced whether or...

Distributed write data drivers for burst access memories

US6381180 (B1), filed Thu Feb 26 00:00:00 CST 1998 , published Tue Apr 30 00:00:00 CDT 2002 - MICRON TECHNOLOGY INC

An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe...

Semiconductor memory device

US5652723 (A), filed Wed Apr 15 00:00:00 CDT 1992 , published Tue Jul 29 00:00:00 CDT 1997 - MITSUBISHI ELECTRIC CORP

A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set...

Distributed write data drivers for burst access memories

US7397711 (B2), filed Thu May 18 00:00:00 CDT 2006 , published Tue Jul 08 00:00:00 CDT 2008 - MICRON TECHNOLOGY INC

An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access...

Semiconductor memory

US4592022 (A), filed Fri Jul 19 00:00:00 CDT 1985 , published Tue May 27 00:00:00 CDT 1986 - HITACHI LTD

A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of...

Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions

US6608791 (B2), filed Mon Mar 25 00:00:00 CST 2002 , published Tue Aug 19 00:00:00 CDT 2003 - HITACHI LTD

A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply...

Large scale integrated circuit for low voltage operation

US5297097 (A), filed Wed Jun 14 00:00:00 CDT 1989 , published Tue Mar 22 00:00:00 CST 1994 - HITACHI LTD

Disclosed is a one-chip ULSI which can carry out fixed operations for a wide range of power supply voltages (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which provides a fixed internal voltage for a wide range of power...

6F2 DRAM array with apparatus for stress testing an isolation gate and method

US6590817 (B2), filed Mon Jul 23 00:00:00 CDT 2001 , published Tue Jul 08 00:00:00 CDT 2003 - MICRON TECHNOLOGY INC

The present invention includes a 6F2 DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation gate is configured to provide electrical isolation between...

Fast and economical establishment of remote copy

US7284105 (B2), filed Wed Sep 10 00:00:00 CDT 2003 , published Tue Oct 16 00:00:00 CDT 2007 - IBM

A storage apparatus is operable as primary in a remote copy pair and comprises a remote copy component operable to establish a remote copy relationship between said primary and a secondary; a copy component operable at the primary to create a copy for download...

Memory device and method having data path with multiple prefetch I/O configurations

US6515914 (B2), filed Wed Mar 21 00:00:00 CST 2001 , published Tue Feb 04 00:00:00 CST 2003 - MICRON TECHNOLOGY INC

A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in...

Differential latching inverter and random access memory using same

US5304874 (A), filed Fri May 31 00:00:00 CDT 1991 , published Tue Apr 19 00:00:00 CDT 1994 - THUNDERBIRD TECH INC

A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation....

Computerized system for operator interaction

US4121284 (A), filed Mon Sep 11 00:00:00 CDT 1972 , published Tue Oct 17 00:00:00 CDT 1978 - HYATT GILBERT P

A system is provided for operator interaction having a computer for enhanced operation. The computer performs switch debounce operations under program control and performs display refresh operations under program control. The computer is a fully integrated...

Asynchronously-resettable decoder with redundancy

US6724681 (B2), filed Fri Feb 02 00:00:00 CST 2001 , published Tue Apr 20 00:00:00 CDT 2004 - BROADCOM CORP

A decoder providing asynchronous reset, redundancy, or both an asynchronously-resettable decoder with redundancy. The decoder has a synchronous portion, responsive to a clocked signal; an asynchronous portion coupled with an asynchronous circuit; a feedback-re...

Multiple bit output dynamic random-access memory

US4406013 (A), filed Wed Oct 01 00:00:00 CDT 1980 , published Tue Sep 20 00:00:00 CDT 1983 - INTEL CORP

A dynamic MOS random-access memory is described which includes a circuit for permitting checking of the on chip refresh counter. The memory also includes a refresh generator, the frequency of which automatically varies to compensate for temperature variations....

Nonvolatile semiconductor memory device

US6438036 (B2), filed Tue Apr 10 00:00:00 CDT 2001 , published Tue Aug 20 00:00:00 CDT 2002 - HITACHI LTD

An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith. The erasing operation is automatically performed by the...

Method of compensating for a defect within a semiconductor device

US6469944 (B2), filed Mon Dec 11 00:00:00 CST 2000 , published Tue Oct 22 00:00:00 CDT 2002 - MICRON TECHNOLOGY INC

As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's...

Low power memory module using restricted RAM activation

US6625049 (B2), filed Thu Dec 20 00:00:00 CST 2001 , published Tue Sep 23 00:00:00 CDT 2003 - MICRON TECHNOLOGY INC

A memory module for an electronic device is disclosed which provides means for reducing the amount of power necessary to access a desired number of data bits. This provides a design of memory modules which requires fewer DRAMs to be turned on during a read or...

Vertically stacked field programmable nonvolatile memory and method of fabrication

US6185122 (B1), filed Wed Dec 22 00:00:00 CST 1999 , published Tue Feb 06 00:00:00 CST 2001 - MATRIX SEMICONDUCTOR INC

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps...

Programmable low impedance anti-fuse element

US4823181 (A), filed Fri May 09 00:00:00 CDT 1986 , published Tue Apr 18 00:00:00 CDT 1989 - ACTEL CORP

An electrically programmable low impedance circuit element is disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming. The electrically programmable low impedance circuit element of the present...

Electrically erasable, directly overwritable, multibit single cell memory element and arrays fabricated therefrom

US5536947 (A), filed Tue Jul 25 00:00:00 CDT 1995 , published Tue Jul 16 00:00:00 CDT 1996 - ENERGY CONVERSION DEVICES INC

An electrically operated, directly overwritable, multibit, single-cell memory element. The memory element includes a volume of memory material which defines the single cell memory element. The memory material is characterized by: (1) a large dynamic range of...

Memory and method for sensing sub-groups of memory elements

US5748554 (A), filed Fri Dec 20 00:00:00 CST 1996 , published Tue May 05 00:00:00 CDT 1998 - RAMBUS INC

A memory and method of operation is described. In one embodiment, the memory includes a group of memory cells divided into a plurality of sub-groups. Sub word-lines are selectively coupled to main word lines, each sub-word line corresponding to a sub-group and...

Reprogrammable subscriber terminal

US7240217 (B2), filed Wed Jul 14 00:00:00 CDT 2004 , published Tue Jul 03 00:00:00 CDT 2007 - SCIENTIFIC ATLANTA

A reprogrammable subscriber terminal of a subscription television service which can have the control program code of its control processor modified by downloading new program code from the headend. The control processor stores a boot program in an internal...

Top 100 US Patents in Static Storage

section g - physics > information storage > static stores