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US2007247920 (A1), filed Jun 26, 2007 , published Oct 25, 2007 - YAMAZOE TAKANORI

The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency...

Data processing device

US2007274129 (A1), filed Jun 29, 2007 , published Nov 29, 2007 - YAMAZOE TAKANORI

A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors...

DATA PROCESSING DEVICE

US2008137429 (A1), filed Jan 09, 2008 , published Jun 12, 2008 - YAMAZOE TAKANORI

A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors...

Semiconductor integrated circuit device, contactless electronic device, and handheld terminal

US2006076626 (A1), filed Oct 11, 2005 , published Apr 13, 2006 - WATANABE KAZUKI

In a semiconductor integrated circuit device in which a rectifier device constituting a rectifier comprises a MOS transistor whose gate is connected to one antenna terminal and whose source is connected to the other antenna terminal, the parasitic capacitance...

NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE

US2008019162 (A1), filed Jun 05, 2007 , published Jan 24, 2008 - MIHARA MASAAKI

This non-volatile semiconductor storage device includes a flip-flop in which two inverters, each consisting of a load transistor and a storage transistor connected in series, are cross-connected; and two gate transistors, each respectively connected to a node...

Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions

US2005219935 (A1), filed May 20, 2005 , published Oct 06, 2005 - ITOH KIYOO

A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply...

Disk processing apparatus with voltage generating circuit having a boost ratio control

US7411831 (B2), filed Jun 26, 2007 , published Aug 12, 2008 - RENESAS TECH CORP

The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency...

Non volatile semiconductor memory device

US7212441 (B2), filed Nov 15, 2005 , published May 01, 2007 - RENESAS TECH CORP

In a nonvolatile semiconductor memory device, the increase of the capacity of a nonvolatile semiconductor memory inevitably causes the power supply circuits including the charge pump circuits at the periphery to increase. In view of the above situation, the...

Semiconductor integrated circuit device, contactless electronic device, and handheld terminal

US7245513 (B2), filed Oct 11, 2005 , published Jul 17, 2007 - RENESAS TECH CORP

In a semiconductor integrated circuit device in which a rectifier device constituting a rectifier comprises a MOS transistor whose gate is connected to one antenna terminal and whose source is connected to the other antenna terminal, the parasitic capacitance...

Nonvolatile memory with multi-frequency charge pump control

US7251162 (B2), filed Apr 27, 2005 , published Jul 31, 2007 - RENESAS TECH CORP

The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency...

Data processing device

US7254084 (B2), filed May 27, 2005 , published Aug 07, 2007 - RENESAS TECH CORP

A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors...

Data processing device

US2006114737 (A1), filed May 27, 2005 , published Jun 01, 2006 - RENESAS TECH CORP

A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors...

Non volatile semiconductor memory device

US2006140003 (A1), filed Nov 15, 2005 , published Jun 29, 2006 - RENESAS TECH CORP

In a nonvolatile semiconductor memory device, the increase of the capacity of a nonvolatile semiconductor memory inevitably causes the power supply circuits including the charge pump circuits at the periphery to increase. In view of the above situation, the...

Data processing device

US7385853 (B2), filed Jun 29, 2007 , published Jun 10, 2008 - RENESAS TECH CORP

A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors...

DATA PROCESSING APPARATUS

US2008279011 (A1), filed Jul 11, 2008 , published Nov 13, 2008 - RENESAS TECH CORP

The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency...