Patents
Patent data provided by The
European Patent Office
and updated through early 2009. Full text patent data loaded weekly coming soon.
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US2005219922 (A1), filed
May 31, 2005
, published
Oct 06, 2005
- HORIGUCHI MASASHI
Method for manufacturing a memory device, the memory being a memory array with a spare bit line and being provided with a defect recovery scheme featuring a redundancy circuit. The redundancy circuit includes one or more comparing circuits having programmable...
US4021835 (A), filed
Jan 27, 1975
, published
May 03, 1977
- HITACHI LTD
A MOS-FET (Metal-Oxide-Semiconductor Field Effect Transistor) comprises a semiconductor body, source and drain regions disposed in the body at portions separated from each other, a second semiconductor region having a higher impurity concentration than that of...
USRE40132 (E1), filed
May 25, 2001
, published
Mar 04, 2008
- ELPIDA MEMORY INC
Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power...
US4635146 (A), filed
Mar 20, 1984
, published
Jan 06, 1987
- VICTOR COMPANY OF JAPAN
An automatic tape loading type recording and/or reproducing apparatus comprises a mechanism for loading a tape in a predetermined path in which the tape makes contact with a guide drum by intercepting and drawing the tape out of the tape cassette, a mechanism...
US4716313 (A), filed
Jun 03, 1987
, published
Dec 29, 1987
- HITACHI LTD
In order to drive a capacitance load at a high speed without an undesirably large increase in the circuit size, a driving arrangement is provided to charge the capacitance load in accordance with a limited voltage. A voltage limiter is coupled to a supply...
US2002031024 (A1), filed
Nov 26, 2001
, published
Mar 14, 2002
A semiconductor memory featuring a defect recovery scheme through employing a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit...
US4992985 (A), filed
Mar 07, 1989
, published
Feb 12, 1991
- HITACHI LTD
US5384740 (A), filed
Dec 21, 1993
, published
Jan 24, 1995
- HITACHI LTD
An apparatus includes a constant voltage generator for generating a voltage based on a difference between threshold voltages of two MOS transistors, and a voltage sampling device for sampling the output voltage of the constant voltage generator circuit,...
US5455797 (A), filed
Oct 04, 1994
, published
Oct 03, 1995
- HITACHI LTD
An apparatus includes a constant voltage generator for generating a voltage based on a difference between threshold voltages of two MOS transistors, and a voltage sampling device for sampling the output voltage of the constant voltage generator circuit,...
US5815448 (A), filed
Mar 31, 1997
, published
Sep 29, 1998
- HITACHI LTD
A redundancy technique is introduced for a semiconductor memory and, more particularly, a redundancy technique for a dynamic random access memory (DRAM) having a storage capacity of 16 mega bits or more. In such a DRAM, the memory array is divided into memory...
US2003189845 (A1), filed
Mar 31, 2003
, published
Oct 09, 2003
A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit...
US4475181 (A), filed
Jan 05, 1982
, published
Oct 02, 1984
- HITACHI LTD
A semiconductor memory of multiplexed address inputs is made operative to receive column addresses and row addresses through common external address lines and to decode them consecutively in response to first and second strobe signals thereby to select one of...
US4965769 (A), filed
Nov 30, 1988
, published
Oct 23, 1990
- HITACHI LTD
A semiconductor memory having a plurality of word lines, and a plurality of data lines arranged to intersect the word lines. Memory cells are arranged at nodes of the word lines and the data lines. Each of the memory cells has a field effect transistor and a...
US5117393 (A), filed
Jan 31, 1991
, published
May 26, 1992
- HITACHI LTD
US5265055 (A), filed
Dec 27, 1991
, published
Nov 23, 1993
- HITACHI LTD
A redundancy technique is introduced for a semiconductor memory and, more particularly a redundancy technique for a dynamic random access memory (DRAM) having a storage capacity of 16 mega bits or more. In such a DRAM, the efficiency of the redundancy...
