Semiconductor memory device having diagnostic circuit for comparing multi-bit read-out test data signal with multi-bit write-in test data signal stored in serial-input shift register - Patent US5406566(A)
Filed:
Oct 22, 1993
Published:
Apr 11, 1995
Abstract
A dynamic random access memory device is subjected to a diagnosis upon completion of fabrication to see whether or not a defective memory cell is incorporated in memory cell sub-arrays, one of the input/output data buffer circuits incorporated therein transfers test bits in serial to a shift register which in turn transfers the test bits in parallel to data line pairs for writing the test bits into the memory cell sub-arrays, and a comparator compares the test bits read out from the memory cell sub-arrays with the test bit stored in the shift register for producing a diagnostic signal indicative of consistence or inconsistence between the test bits read out from the memory cell sub-arrays and the test bits in the shift register, thereby allowing an external diagnostic system with data pins less than the input/output data buffer circuits to carry out the diagnosis.Applicants
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NIPPON ELECTRIC CO
Inventors
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OBARA TAKASHI
Application Number
139717Priority Claims
JP28722992Family Members
JP6139798(A) -
SEMICONDUCTOR MEMORY
US5406566(A) -
Semiconductor memory device having diagnostic circuit for comparing multi-bit read-out test data signal with multi-bit write-in test data signal stored in serial-input shift register
